With CDMA, a signal transmission is performed by spreading an input signal using channelization codes and scrambling codes. This ratio of bandwidths of a transmission signal and an input signal is called a spreading factor (SF) in CDMA. The channelization code is used for distinguishing a channel; the scrambling code is used for distinguishing a user.
In drawings explained below, the same numeral signs (for example, 100) are used for the same parts or corresponding parts. To differentiate each of the same parts or the corresponding parts, a sign consisting of a numeral sign and an alphabetical sign (for example, 100a, 100b) is used. FIG. 29 shows an explanatory drawing of a multiplexing transmission of uplink data channels when a communication apparatus described in 3GPP (3rd Generation Partnership Project) transmits data to a base station. At least one DPDCH (Dedicated Physical Data Channel), one DPCCH (Dedicated Physical Control Channel), a high-speed control channel for HS-DSCH (Dedicated Physical Control Channel for HS-DSCH (High Speed Downlink Shared Channel): HS-DPCCH) are multiplexed and transmission is carried out.
A communication apparatus of FIG. 29 shows a detailed configuration of a modulating unit 902 illustrated in FIG. 1, which processes IQ multiplexing of plural data channels and control channels of an I side and a Q side to generate a complex signal. FIG. 29 includes multipliers 100a through 100c at the I side and 100e through 100g at the Q side which multiply spread codes (channelization codes) Cd,1 through Cd,6 for separating channels to data of DPDCH1 through DPDCH6 which are data channels, a multiplier 100h at the Q side which multiplies a spread code Cc for separating channels to control data of the control channel DPCCH, a multiplier 100d at the I side and a multiplier 100i at the Q side which multiply a spread code Chs for separating channels to control data of a newly added control channel HS-DPCCH. Further, multipliers 101a through 101c at the I side and 101e through 101g at the Q side which multiply an amplitude factor β d for DPDCHs to output signals from the multipliers 100a through 100c at the I side and multipliers 100e through 100g at the Q side are provided; a multiplier 101h which multiplies an amplitude factor β c for a DPCCH to output signals from the multiplier 100h at the Q side is provided; and multipliers 101d and 101i which multiplies an amplitude factor β hs for an HS-DPCCH to output signals from the multiplier 100d at the I side and the multiplier 100i at the Q side are provided. Yet further, an adder 102a for adding outputs signals from the multipliers 101a through 101d at the I side, an adder 102b for adding output signals from the multipliers 101e through 101i at the Q side, a multiplier 103 for multiplying an imaginary number j to an output signal from the adder 102b at the Q side, an adder 104 for carrying out a complex addition of outputs from the adder 102a at the I side and the multiplier 103 at the Q side, and a multiplier 105 for multiplying a scrambling code Sdpch,n to an output signal from the adder 104 are included.
Next, an operation will be explained. To each channel, the multiplier 100 multiplies a channelization code CSF,k. Here, SF shows a spreading factor, and k shows a code number. It is assumed that N is a multiplexing number. To multiplex DPDCHs having the multiplexing number N(N≧2), channelization codes are determined for each channel as follows: The channelization code for a DPCCH is C256,0. The channelization codes for an HS-DPCCH are C256,1 (N=2, 4, 6) and C256,32 (N=3, 5). The channelization code for DPDCHx (DPDCHx: x is a channel number) is C4,1 (x=1, 2), C4,3 (x=3, 4), and C4,2 (x=5, 6). Next, the multiplier 101 carries out weighing. β shows a weighing function, which is a gain factor whose weight varies according to a kind of channel. These are added by an accumulator (an adder 102). Then, the multiplier 103 and an adder 104 are used to make a transmission signal a complex number. Finally, the multiplier 105 multiplies it by a scrambling code Sdpch,n to carry out transmission.
Transmission is carried out using HPSK (Hybrid Phase Shift Keying) modulation in 3GPP. In HPSK modulation, a signal output from a configuration shown in FIG. 30 is used as the scrambling code. W0 and W1 have repeated patterns of W0=[1,1] and W1=[1,−1], respectively, and are referred to as Walsh Rotators. Clong,1,n and Clong,2,n are Gold Sequences having different phases, respectively. First, a decimating unit 200 decimates an even-numbered chip of Clong,2,n, and an odd-numbered chip that is located directly before is inserted instead of the decimated chip. Next, the multiplier 201 multiplies a signal output from the decimating unit 200 and W1. Then, it is made to be a complex number by the multiplier 202 and the adder 203. Finally, Clong,1,n is multiplied by the multiplier 204. At this time, as a complex signal input to the multiplier 204, a complex number is input to an even-numbered chip which is conjugate with an odd-numbered chip. By multiplying an output scrambling code Sdpch,n to this signal, a phase variation from an odd-numbered chip to an even-numbered chip always becomes 90 degrees when the signal input to the multiplier 105, that is, multiplexed signal, has the same phase continuously.
FIG. 31 shows a tracking of the transmitted chip on a complex plane. A phase of the chip in this explanation means a phase of a point on the complex plane as shown in FIG. 31, and a phase variation means a variation of phase angles during a transition among the chips. As shown in the figure, when the phase variation is 0 degrees or 180 degrees, a peak value of an amplitude becomes large because of overshoot, which affects an amplifier badly. Further, it is understood that when the phase variation is 90 degrees, the peak does not increase and the phase variation is ideal. Accordingly, when it is considered that the phase rotates by 90 degrees by the scrambling code, the phase variation from an odd-numbered chip to an even-numbered chip is desired to be 0 degrees or 180 degrees at a stage of multiplexing the data channels before applying the scrambling code. A method to resolve the overshoot using only the channelization code CSF,k of which 0≦k≦SF/2−1 or only the channelization code CSF,k of which (SF/2) ≦k≦(SF−1) is disclosed in JP2002-33716 as a code assignment method in consideration of the phase variation from an odd-numbered chip to an even-numbered chip.
JP2002-33716 (Patent document 1) notices that SF is 4 and selects a combination so that the phase variations both from the first chip to the second chip and from the third chip to the fourth chip should be 0 degrees or 180 degrees when one piece of data is spread. Further, this patent document 1 assumes that, by using that the gain factor of a DPCCH is very small, the DPCCH does not affect the phase variation. FIG. 32 shows a case of using only the channelization code C4,k of which 0≦k≦1 when the number of multiplexed DPDCHs is three. FIG. 33 shows a case of using only the channelization code C4,k of which 2≦k≦3 when the number of multiplexed DPDCHs is three, and FIG. 34 shows a case in which the number of multiplexed DPDCHs is four. When C4,2 is assigned to DPDCH1, C4,2 is assigned to DPDCH2, and C4,3 is assigned to DPDCH3 as shown in FIG. 33, chips output from the IQ become as follows:I=(2, −2, 0, 0)Q=(1, −1, 1, −1)
Here, the phase variation from the first chip to the second chip is 180 degrees, and the phase variation from the third chip to the fourth chip is also 180 degrees. Accordingly, this assignment of the channelization codes is ideal.
This method, however, can use only one of combinations of the channelization C4,0 and C4,1, or the channelization codes C4,2 and C4,3, so that this method cannot be applied to a case in which the number of multiplexed DPDCHs is at least five. Further, only one of the combinations of C4,0 and C4,1 and C4,2 and C4,3 can be used, only a case when the phase variation is 0 degrees or 180 degrees is considered. Accordingly, when the phase variation does not become 0 degrees or 180 degrees, it is not considered how much the phase variation should be set. Further, since only a DPCCH and a DPDCH are considered, there is a problem that the method cannot be applied to a case including another channel such as an HS-DPCCH. For example, it is assumed that an HS-DPCCH having the gain whose magnitude is the same as a DPDCH is added to the example of FIG. 33. In case of the number of multiplexing N=3, since the channelization code for the HS-DPCCH is C256,32, (1, 1, 1, 1) or (−1, −1, −1, −1) is input, when it is considered by 4-chip unit. For example, in case of (1, 1, 1, 1), chips output from the IQ become:I=(2, −2, 0, 0)Q=(1, −1, 1, −1)+(1, 1, 1, 1)=(2, 0, 2, 0)The phase variation from the first chip to the second chip is 135 degrees and the phase variation from the third chip to the fourth chip is not known, since it passes the point of origin. As a result, it cannot be said that the channelization codes are assigned optimally.
In the next specification, Release 6 (Rel-6), introduction of uplink enhancement is considered. In the uplink enhancement, other than the conventional transport channel DCH (Dedicated Channel), E-DCH (Enhanced Dedicated Channel) is also superimposed on a DPDCH. Further, it has been considered to introduce an E-DPCCH (Enhanced DPCCH). FIGS. 35 and 36 show examples of multiplexing transmission of uplink data channels in the uplink enhancement. A broken line in the figure shows that the transmission may not exist depending on the number of multiplexed channels. In FIG. 35, DPDCHs superimpose DCH or E-DCH, and an E-DPCCH is treated as one control channel. Further, only for DPDCH1 it is determined that DCH is superimposed on it. Further, in FIG. 36, multiplexing is done so that DCH, E-DCH, and E-DPCCH are superimposed only on DPDCH1, and DCH and E-DCH are superimposed on other DPDCHs. Besides, various ways of multiplexing are proposed. Here, since the data amount of a DPDCH that superimposes E-DCH or an E-DPCCH is large, their gain factor becomes larger than that of a DPDCH that superimposes only DCH.    Patent Document 1: JP2002-33716    Non-patent Document 1: 3GPP Technical Report TR25.896 v1.2.1